This application claims priority from Korean Patent Application No. 2003-84961, filed on Nov. 27, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same, more particularly, to a semiconductor memory device with storage electrodes and a method of manufacturing the same.
2. Description of the Related Art
As the integration density of semiconductor devices has increased, the design rule of the semiconductor devices has reduced. More specially, pitches between electrodes in a capacitor of a memory device such as dynamic random access memory (DRAM), have gradually been reduced for rapid advancement of high integration and scaling of the memory device. Unfortunately, reducing the pitches to meet design rules is undesirable because it also reduces capacitance and semiconductor memory devices require a high capacitance in order to operate smoothly without problems like soft errors.
There are options to increase capacitance. Enlarging the surface area of a storage electrode (a capacitor lower electrode), decreasing the thickness of a dielectric layer, and using a dielectric layer with a high dielectric constant are methods of increasing the capacitance of the capacitor. Among these methods, enlarging the surface area of the storage electrode is most commonly used, including maximizing the height of a cylindrical capacitor.
A storage electrode with a cylindrical shape has been manufactured with the following method. First, a mold oxide layer with the same height as a predetermined height of a storage electrode may be formed on the upper surface of a semiconductor substrate whereon a semiconductor circuit, for example, a MOS transistor, is formed. A photoresist pattern is formed on the upper surface of the mold oxide layer using a conventional photolithography process so that the predetermined region of the storage electrode is exposed. After the storage electrode region is defined by etching the mold oxide layer using the photoresist pattern, the photoresist pattern is removed. Then an electrode material is adhered on the patterned mold oxide layer and planarized, thereby exposing the surface of the mold oxide layer forming the storage electrode with a cylindrical shape.
The desire for highly-integrated semiconductor memory device has required capacitor height to increase significantly in order to secure the large capacitance. Therefore, the mold oxide layer defining the height of the storage electrode has been formed with a thickness of 1.5 to 2 μm. As will be explained, this increased thickness has created new challenges.
Parts of the photoresist pattern are eliminated by an etching gas used for etching the mold oxide layer because the photoresist pattern has a low etch selectivity with respect to the mold oxide layer. However, when the thickness of the mold oxide layer is increased, the photoresist pattern can become deformed. Therefore, the shape of the photoresist pattern is changed, and if the mold oxide layer is etched using the photoresist pattern, as described above, the shape of the storage electrode region is also changed. Such a phenomenon is referred to as striation. Therefore, a desirable form of the storage electrode region has been difficult to secure.
To prevent defects like the striation, a hard mask layer has been conventionally used instead of the photoresist pattern. Referring to FIGS. 1 and 2, a method of forming the storage electrode using the hard mask layer will now be described.
Referring to FIG. 1, a mold oxide layer 20 is formed on the upper surface of a semiconductor substrate 10 where a circuit device (not shown) is formed. A polysilicon layer 30, to be used as a mask layer, is adhered on the upper surface of the mold oxide layer 20, and a silicon nitride layer 40, to be used as an anti-reflection layer, is adhered on the upper surface of the polysilicon layer 30. A photoresist pattern (not shown) defining a storage electrode, is formed on the upper surface of the silicon nitride layer 40. The silicon nitride layer 40 and the polysilicon layer 30 are then etched using the photoresist pattern as an etch mask, and a hard mask pattern 50 is formed. Next, the photoresist pattern is removed.
Referring to FIG. 2, the mold oxide layer 20 is then dry etched using the hard mask pattern 50 as an etch mask, thereby forming a storage electrode region 60. Then, a conductive layer is adhered in the storage electrode region 60 and on the surface of the mold oxide layer 20. Next, the conductive layer is planarized to form a storage electrode 70 in the storage electrode region 60.
However, when the storage electrode region is formed using the hard mask pattern including the polysilicon layer 30 and the silicon nitride layer 40, a curved surface A of the sidewalls of the mold oxide defining the storage electrode region 60 may occur.
The following describes the cause of the curved surface A.
Generally, when the photoresist pattern is used as the mask, the etching gas for etching the mold oxide layer 20, which is a fluorocarbon compound, reacts with elements of the photoresist pattern, generating etching residual products, or polymers, on sidewalls of the storage electrode region 60. Etching residual products remaining on the sidewalls of the storage electrode region 60 may protect the sidewalls of the storage electrode region 60, even though the etching gas is ion scattered an angle to the sidewalls.
However, the hard mask pattern 50 including the polysilicon layer 30 and the silicon nitride layer 40 hardly react with the etching gas that is a fluorocarbon compound, thereby etching residual products on the sidewalls of the storage electrode region 60 are hardly generated. Therefore, when the etching gas is ion scattered an angle to the sidewalls, portions of the sidewalls of the storage electrode region 60 are etched (removed), the curved surfaces A occur as shown in FIGS. 2 and 3.
If the storage electrode 70 is formed with the curved surface A in the storage electrode region 60, and the mold oxide layer 20 is removed by wet cleaning, the resultant storage electrode 70 collapses and contacts an adjacent storage electrode 70 because of the surface tension of the storage electrode 70. Thus, leaning and bit fails of the storage electrode 70 can occur, causing the resulting device to function improperly.
Embodiments of the invention address these and other limitations in the prior art.